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MT48LC4M32B2P-6A IT - 

SDRAM, 4M x 32bit, 6 ns, TSOP-II-86

MICRON MT48LC4M32B2P-6A IT

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Fabricante:
MICRON MICRON
Nº da peça do fabricante:
MT48LC4M32B2P-6A IT
Código Farnell
2253746
Ficha técnica:
(EN)
Ver todos os documentos técnicos

Informação do produto

:
-40°C
:
85°C
:
6ns
:
4M x 32bit
:
86Pins
:
-
:
TSOP-II
:
-
:
Each
:
-
:
MSL 3 - 168 hours
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Descrição geral do produto

The MT48LC4M32B2P-6A IT is a SDR SDRAM with high-speed CMOS and uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed and random-access operation. This is a high-speed CMOS, dynamic random-access memory containing 134217728-bits. It is internally configured as a quad-bank DRAM with a synchronous interface. Read and write accesses to the SDRAM is burst-oriented, accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an active command, which is then followed by a read or write command.
  • PC100-compliant
  • Fully synchronous, all signals registered on positive edge of system clock
  • Internal banks for hiding row access/precharge
  • Auto precharge, includes concurrent auto precharge and auto refresh modes
  • Self refresh mode
  • LVTTL-compatible inputs and outputs

Aplicações

Communications & Networking